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FCMEQ (scalar, zero)

Floating-point Compare Equal to zero (vector).

Syntax

FCMEQ Hd, Hn, #0.0 ; Scalar half precision

FCMEQ Vd, Vn, #0.0 ; Scalar single-precision and double-precision

Where:

Hd
Is the 16-bit name of the SIMD and FP destination register.
Hn
Is the 16-bit name of the SIMD and FP source register.
V
Is a width specifier, and can be either S or D.
d
Is the number of the SIMD and FP destination register.
n
Is the number of the SIMD and FP source register.

Architectures supported (scalar)

Supported in ARMv8.2 and later.

Usage

Floating-point Compare Equal to zero (vector). This instruction reads each floating-point value in the source SIMD and FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD and FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD and FP register to zero.

This instruction can generate a floating-point exception. Depending on the settings in FPCR in the ARMv8-A Architecture Reference Manual, the exception results in either a flag being set in FPSR in the ARMv8-A Architecture Reference Manual, or a synchronous exception being generated. For more information, see Floating-point exception traps in the ARMv8-A Architecture Reference Manual.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

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