Signed saturating Shift Right Narrow (immediate).
- Is the destination width specifier, and can be one of the values shown in Usage.
- Is the number of the SIMD and FP destination register.
- Is the source width specifier, and can be one of the values shown in Usage.
- Is the number of the first SIMD and FP source register.
- Is the right shift amount, in the range 1 to the destination operand width in bits, and can be one of the values shown in Usage.
Signed saturating Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD and FP register, right shifts and truncates each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD and FP register. All the values in this instruction are signed integer values. The destination vector elements are half as long as the source vector elements. For rounded results, see SQRSHRN in the ARMv8-A Architecture Reference Manual.
SQSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the
SQSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.
If saturation occurs, the cumulative saturation bit FPSR.QC is set.
Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
The following table shows the valid specifier combinations:
Table 19-26 SQSHRN (Scalar) specifier combinations
|B||H||1 to 8|
|H||S||1 to 16|
|S||D||1 to 32|