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ADDHN, ADDHN2 (vector)

Add returning High Narrow.

Syntax

ADDHN{2} Vd.Tb, Vn.Ta, Vm.Ta

Where:

2
Is the second and upper half specifier. If present it causes the operation to be performed on the upper 64 bits of the registers holding the narrower elements. See <Q> in the Usage table.
Vd
Is the name of the SIMD and FP destination register.
Tb
Is an arrangement specifier, and can be one of the values shown in Usage.
Vn
Is the name of the first SIMD and FP source register.
Ta
Is an arrangement specifier, and can be one of the values shown in Usage.
Vm
Is the name of the second SIMD and FP source register.

Usage

Add returning High Narrow. This instruction adds each vector element in the first source SIMD and FP register to the corresponding vector element in the second source SIMD and FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD and FP register.

The results are truncated. For rounded results, see RADDHN in the ARMv8-A Architecture Reference Manual.

The ADDHN instruction writes the vector to the lower half of the destination register and clears the upper half, while the ADDHN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

The following table shows the valid specifier combinations:

Table 20-2 ADDHN, ADDHN2 (Vector) specifier combinations

<Q> Tb Ta
- 8B 8H
2 16B 8H
- 4H 4S
2 8H 4S
- 2S 2D
2 4S 2D
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