FCMLE (vector, zero)
Floating-point Compare Less than or Equal to zero (vector).
Syntax
FCMLE
Vd.T, Vn.T, #0.0 ; Vector half precision
FCMLE
Vd.T, Vn.T, #0.0 ; Vector single-precision and double-precision
Where:
Vd- Is the name of the SIMD and FP destination register
T-
For the vector half precision variant: is an arrangement specifier:
- Vector half precision
-
Can be one of
4Hor8H. - Vector single-precision and double-precision
-
Can be one of
2S,4Sor2D.
Vn- Is the name of the SIMD and FP source register
Architectures supported (vector)
Supported in ARMv8.2 and later.
Usage
Floating-point Compare Less than or Equal to zero (vector). This instruction reads each floating-point value in the source SIMD and FP register and if the value is less than or equal to zero sets every bit of the corresponding vector element in the destination SIMD and FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD and FP register to zero.
This instruction can generate a floating-point exception. Depending on the settings in FPCR in the ARMv8-A Architecture Reference Manual, the exception results in either a flag being set in FPSR in the ARMv8-A Architecture Reference Manual, or a synchronous exception being generated. For more information, see Floating-point exception traps in the ARMv8-A Architecture Reference Manual.
Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.