FCVTPU (vector)
Floating-point Convert to Unsigned integer, rounding toward Plus infinity (vector).
Syntax
FCVTPU
Vd.T, Vn.T ; Vector half precision
FCVTPU
Vd.T, Vn.T ; Vector single-precision and double-precision
Where:
Vd- Is the name of the SIMD and FP destination register
T-
For the vector half precision variant: is an arrangement specifier:
- Vector half precision
-
Can be one of
4Hor8H. - Vector single-precision and double-precision
-
Can be one of
2S,4Sor2D.
Vn- Is the name of the SIMD and FP source register
Architectures supported (vector)
Supported in ARMv8.2 and later.
Usage
Floating-point Convert to Unsigned integer, rounding toward Plus infinity (vector). This instruction converts a scalar or each element in a vector from a floating-point value to an unsigned integer value using the Round towards Plus Infinity rounding mode, and writes the result to the SIMD and FP destination register.
A floating-point exception can be generated by this instruction. Depending on the settings in FPCR in the ARMv8-A Architecture Reference Manual, the exception results in either a flag being set in FPSR in the ARMv8-A Architecture Reference Manual, or a synchronous exception being generated. For more information, see Floating-point exception traps in the ARMv8-A Architecture Reference Manual.
Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.