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FDIV (vector)

Floating-point Divide (vector).

Syntax

FDIV Vd.T, Vn.T, Vm.T ; Half-precision

FDIV Vd.T, Vn.T, Vm.T ; Single-precision and double-precision

Where:

T

For the half-precision variant: is an arrangement specifier:

Half-precision
Can be one of 4H or 8H.
Single-precision and double-precision
Can be one of 2S, 4S or 2D.
Vd
Is the name of the SIMD and FP destination register.
Vn
Is the name of the first SIMD and FP source register.
Vm
Is the name of the second SIMD and FP source register.

Architectures supported (vector)

Supported in ARMv8.2 and later.

Usage

Floating-point Divide (vector). This instruction divides the floating-point values in the elements in the first source SIMD and FP register, by the floating-point values in the corresponding elements in the second source SIMD and FP register, places the results in a vector, and writes the vector to the destination SIMD and FP register.

This instruction can generate a floating-point exception. Depending on the settings in FPCR in the ARMv8-A Architecture Reference Manual, the exception results in either a flag being set in FPSR in the ARMv8-A Architecture Reference Manual, or a synchronous exception being generated. For more information, see Floating-point exception traps in the ARMv8-A Architecture Reference Manual.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

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