FMINV (vector)
Floating-point Minimum across Vector.
Syntax
FMINV
Vd, Vn.T ; Half-precision
FMINV
Vd, Vn.T ; Single-precision and double-precision
Where:
V-
For the single-precision and double-precision variant: is the destination width specifier:
- Single-precision and double-precision
-
Must be
S. - Half-precision
-
Must be
H.
T-
For the half-precision variant: is an arrangement specifier:
- Half-precision
-
Can be one of
4Hor8H. - Single-precision and double-precision
-
Must be
4S.
d- Is the number of the SIMD and FP destination register.
Vn- Is the name of the SIMD and FP source register.
Architectures supported (vector)
Supported in ARMv8.2 and later.
Usage
Floating-point Minimum across Vector. This instruction compares all the vector elements in the source SIMD and FP register, and writes the smallest of the values as a scalar to the destination SIMD and FP register. All the values in this instruction are floating-point values.
This instruction can generate a floating-point exception. Depending on the settings in FPCR in the ARMv8-A Architecture Reference Manual, the exception results in either a flag being set in FPSR in the ARMv8-A Architecture Reference Manual or a synchronous exception being generated. For more information, see Floating-point exception traps in the ARMv8-A Architecture Reference Manual.
Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.