FRECPS (vector)
Floating-point Reciprocal Step.
Syntax
FRECPS
Vd.T, Vn.T, Vm.T ; Vector half precision
FRECPS
Vd.T, Vn.T, Vm.T ; Vector single-precision and double-precision
Where:
Vd- Is the name of the SIMD and FP destination register
T-
For the vector half precision variant: is an arrangement specifier:
- Vector half precision
-
Can be one of
4Hor8H. - Vector single-precision and double-precision
-
Can be one of
2S,4Sor2D.
Vn- Is the name of the first SIMD and FP source register
Vm- Is the name of the second SIMD and FP source register
Architectures supported (vector)
Supported in ARMv8.2 and later.
Usage
Floating-point Reciprocal Step. This instruction multiplies the corresponding floating-point values in the vectors of the two source SIMD and FP registers, subtracts each of the products from 2.0, places the resulting floating-point values in a vector, and writes the vector to the destination SIMD and FP register.
This instruction can generate a floating-point exception. Depending on the settings in FPCR in the ARMv8-A Architecture Reference Manual, the exception results in either a flag being set in FPSR in the ARMv8-A Architecture Reference Manual, or a synchronous exception being generated. For more information, see Floating-point exception traps in the ARMv8-A Architecture Reference Manual.
Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.