Floating-point Reciprocal Square Root Step.
T ; Vector half precision
T ; Vector single-precision and double-precision
- Is the name of the SIMD and FP destination register
For the vector half precision variant: is an arrangement specifier:
- Vector half precision
Can be one of
- Vector single-precision and double-precision
Can be one of
- Is the name of the first SIMD and FP source register
- Is the name of the second SIMD and FP source register
Architectures supported (vector)
Supported in ARMv8.2 and later.
Floating-point Reciprocal Square Root Step. This instruction multiplies corresponding floating-point values in the vectors of the two source SIMD and FP registers, subtracts each of the products from 3.0, divides these results by 2.0, places the results into a vector, and writes the vector to the destination SIMD and FP register.
This instruction can generate a floating-point exception. Depending on the settings in FPCR in the ARMv8-A Architecture Reference Manual, the exception results in either a flag being set in FPSR in the ARMv8-A Architecture Reference Manual, or a synchronous exception being generated. For more information, see Floating-point exception traps in the ARMv8-A Architecture Reference Manual.
Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.