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SHLL, SHLL2 (vector)

Shift Left Long (by element size).

Syntax

SHLL{2} Vd.Ta, Vn.Tb, #shift

Where:

2
Is the second and upper half specifier. If present it causes the operation to be performed on the upper 64 bits of the registers holding the narrower elements. See <Q> in the Usage table.
Vd
Is the name of the SIMD and FP destination register.
Ta
Is an arrangement specifier, and can be one of the values shown in Usage.
Vn
Is the name of the SIMD and FP source register.
Tb
Is an arrangement specifier, and can be one of the values shown in Usage.
shift
Is the left shift amount, which must be equal to the source element width in bits, and can be one of the values shown in Usage.

Usage

Shift Left Long (by element size). This instruction reads each vector element in the lower or upper half of the source SIMD and FP register, left shifts each result by the element size, writes the final result to a vector, and writes the vector to the destination SIMD and FP register. The destination vector elements are twice as long as the source vector elements.

The SHLL instruction extracts vector elements from the lower half of the source register, while the SHLL2 instruction extracts vector elements from the upper half of the source register.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

The following table shows the valid specifier combinations:

Table 20-40 SHLL, SHLL2 (Vector) specifier combinations

<Q> Ta Tb shift
- 8H 8B 8
2 8H 16B 8
- 4S 4H 16
2 4S 8H 16
- 2D 2S 32
2 2D 4S 32
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