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# TBL (vector)

Table vector Lookup.

### Syntax

``` TBL Vd.Ta, { Vn.16B }, Vm.Ta ; Single register table ```

``` TBL Vd.Ta, { Vn.16B, <Vn+1>.16B }, Vm.Ta ; Two register table ```

``` TBL Vd.Ta, { Vn.16B, <Vn+1>.16B, <Vn+2>.16B }, Vm.Ta ; Three register table ```

``` TBL Vd.Ta, { Vn.16B, <Vn+1>.16B, <Vn+2>.16B, <Vn+3>.16B }, Vm.Ta ; Four register table ```

Where:

`Vn`

The value depends on the instruction variant:

Single register table
For the single register table variant: is the name of the SIMD and FP table register
Two, Three, or Four register table
For the four register table, three register table and two register table variant: is the name of the first SIMD and FP table register
`<Vn+1>`
Is the name of the second SIMD and FP table register.
`<Vn+2>`
Is the name of the third SIMD and FP table register.
`<Vn+3>`
Is the name of the fourth SIMD and FP table register.
`Vd`
Is the name of the SIMD and FP destination register.
`Ta`
Is an arrangement specifier, and can be either `8B` or `16B`.
`Vm`
Is the name of the SIMD and FP index register.

## Usage

Table vector Lookup. This instruction reads each value from the vector elements in the index source SIMD and FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD and FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD and FP register. If an index is out of range for the table, the result for that lookup is 0. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.