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VCMLA (by element)

Vector Complex Multiply Accumulate (by element).

Syntax

VCMLA{q}.F16 Dd, Dn, Dm[index], #rotate ; A1 Double,halfprec FP/SIMD registers (A32)

VCMLA{q}.F32 Dd, Dn, Dm[0], #rotate ; A1 Double,singleprec FP/SIMD registers (A32)

VCMLA{q}.F32 Qd, Qn, Dm[0], #rotate ; A1 Quad,singleprec FP/SIMD registers (A32)

VCMLA{q}.F16 Qd, Qn, Dm[index], #rotate ; A1 Halfprec,quad FP/SIMD registers (A32)

VCMLA{q}.F16 Dd, Dn, Dm[index], #rotate ; T1 Double,halfprec FP/SIMD registers (T32)

VCMLA{q}.F32 Dd, Dn, Dm[0], #rotate ; T1 Double,singleprec FP/SIMD registers (T32)

VCMLA{q}.F32 Qd, Qn, Dm[0], #rotate ; T1 Quad,singleprec FP/SIMD registers (T32)

VCMLA{q}.F16 Qd, Qn, Dm[index], #rotate ; T1 Halfprec,quad FP/SIMD registers (T32)

Where:

q
See Standard assembler syntax fields in the ARMv8-A Architecture Reference Manual.
Dd
Is the 64-bit name of the SIMD and FP destination register.
Dn
Is the 64-bit name of the first SIMD and FP source register.
Dm
Is the 64-bit name of the second SIMD and FP source register
index
Is the element index in the range 0 to 1.
rotate
Is the rotation to be applied to elements in the second SIMD and FP source register. For the Double,halfprec FP/SIMD registers, can be one of 0, 90, 180 or 270.
Qd
Is the 128-bit name of the SIMD and FP destination register.
Qn
Is the 128-bit name of the first SIMD and FP source register.

Architectures supported

Supported in ARMv8.3.

Usage

Depending on settings in the CPACR in the ARMv8-A Architecture Reference Manual, NSACR in the ARMv8-A Architecture Reference Manual, and HCPTR in the ARMv8-A Architecture Reference Manual registers, and the security state and mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support in the ARMv8-A Architecture Reference Manual.

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