FCMLA (scalar, by element)
Floating-point Complex Multiply Accumulate (by element).
- Is the name of the SIMD and FP destination register.
- Is an arrangement specifier, and can be one of the values shown in Usage.
- Is the name of the first SIMD and FP source register.
- Is the name of the second SIMD and FP source register in the range 0 to 31.
Is an element size specifier, and can be either
- Is the element index, in the range shown in Usage.
- Is the rotation, and can be one of the values shown in Usage.
Architectures supported (scalar)
Supported in the Arm®v8.3-A architecture and later.
This instruction multiplies the two source complex numbers from the
Vm and the
Vn vector registers and adds the result to the corresponding complex number in the destination
Vd vector register. The number of complex numbers that can be stored in the
Vn, and the
Vd registers is calculated as the vector register size divided by the length of each complex number. These lengths are 16 for half-precision, 32 for single-precision, and 64 for double-precision. Each complex number is represented in a SIMP&FP register as a pair of elements with the imaginary part of the number being placed in the more significant element, and the real part of the number being placed in the less significant element. Both real and imaginary parts of the source and the resulting complex number are represented as floating-point values.
None, one, or both of the two vector elements that are read from each of the numbers in the
Vm source SIMD and FP register can be negated based on the rotation value:
- If the rotation is 0, none of the vector elements are negated.
- If the rotation is 90, the odd-numbered vector elements are negated.
- If the rotation is 180, both vector elements are negated.
- If the rotation is 270, the even-numbered vector elements are negated.
The indexed element variant of this instruction is available for half-precision and single-precision number values. For this variant, the index value determines the position in the
Vm source vector register of the single source value that is used to multiply each of the complex numbers in the
Vn source vector register. The index value is encoded as H:L for half-precision values, or H for single-precision values.
This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps in the Arm® Architecture Reference Manual Arm®v8, for Arm®v8‑A architecture profile.
Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
The following table shows the valid specifier combinations:
Table 19-3 FCMLA (Scalar) specifier combinations