FCVTL, FCVTL2 (vector)
Floating-point Convert to higher precision Long (vector).
- Is the second and upper half specifier. If present it causes the operation to be performed on the upper 64 bits of the registers holding the narrower elements. See <Q> in the Usage table.
- Is the name of the SIMD and FP destination register.
Is an arrangement specifier, and can be either
- Is the name of the SIMD and FP source register.
- Is an arrangement specifier, and can be one of the values shown in Usage.
Floating-point Convert to higher precision Long (vector). This instruction reads each element in a vector in the SIMD and FP source register, converts each value to double the precision of the source element using the rounding mode that is determined by the FPCR, and writes each result to the equivalent element of the vector in the SIMD and FP destination register.
Where the operation lengthens a 64-bit vector to a 128-bit vector, the
FCVTL2 variant operates on the elements in the top 64 bits of the source register.
This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps in the Arm® Architecture Reference Manual Arm®v8, for Arm®v8‑A architecture profile.
Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
The following table shows the valid specifier combinations:
Table 20-7 FCVTL, FCVTL2 (Vector) specifier combinations