SCVTF (vector, fixed-point)
Signed fixed-point Convert to Floating-point (vector).
- Is the name of the SIMD and FP destination register.
- Is an arrangement specifier, and can be one of the values shown in Usage.
- Is the name of the SIMD and FP source register.
- Is the number of fractional bits, in the range 1 to the element width.
Signed fixed-point Convert to Floating-point (vector). This instruction converts each element in a vector from fixed-point to floating-point using the rounding mode that is specified by the FPCR, and writes the result to the SIMD and FP destination register.
This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps in the Arm® Architecture Reference Manual Arm®v8, for Arm®v8‑A architecture profile.
Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
The following table shows the valid specifier combinations:
Table 20-42 SCVTF (Vector) specifier combinations
|2S||1 to 32|
|4S||1 to 32|
|2D||1 to 64|