dreglist ; A1 Decrement Before FP/SIMD registers (A32)
dreglist ; A1 Increment After FP/SIMD registers (A32)
dreglist ; T1 Decrement Before FP/SIMD registers (T32)
dreglist ; T1 Increment After FP/SIMD registers (T32)
- Is an optional instruction condition code. See Chapter 7 Condition Codes.
- Is an optional instruction width specifier. See Instruction width specifiers.
- Is the general-purpose base register. If writeback is not specified, the PC can be used.
- Specifies base register writeback.
- Is the list of consecutively numbered 64-bit SIMD and FP registers to be transferred. The list must contain at least one register, all registers must be in the range D0-D15, and must not contain more than 16 registers.
FLDMX loads multiple SIMD and FP registers from consecutive locations in the Advanced SIMD and floating-point register file using an address from a general-purpose register.
Arm deprecates use of FLDMDBX and FLDMIAX, except for disassembly purposes, and reassembly of disassembled code.
Depending on settings in the CPACR, NSACR, and HCPTR registers, and the security state and mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support in the Arm® Architecture Reference Manual Arm®v8, for Arm®v8‑A architecture profile.