Extension register bank mapping for Advanced SIMD in AArch32 state
The Advanced SIMD extension register bank is a collection of registers that can be accessed as either 64-bit or 128-bit registers.
Advanced SIMD and floating-point instructions use the same extension register bank, and is distinct from the Arm® core register bank.
The following figure shows the views of the extension register bank, and the
overlap between the different size registers. For example, the 128-bit register
Q0 is an alias for two consecutive 64-bit registers
D0 and D1. The 128-bit register
Q8 is an alias for 2 consecutive 64-bit registers
Figure 9-1 Extension register bank for Advanced SIMD in AArch32 state
NoteIf your processor supports both Advanced SIMD and floating-point, all the Advanced SIMD registers overlap with the floating-point registers.
The aliased views enable half-precision, single-precision, and double-precision values, and Advanced SIMD vectors to coexist in different non-overlapped registers at the same time.
You can also use the same overlapped registers to store half-precision, single-precision, and double-precision values, and Advanced SIMD vectors at different times.
Do not attempt to use overlapped 64-bit and 128-bit registers at the same time because it creates meaningless results.
The mapping between the registers is as follows:
D<2n>maps to the least significant half of
D<2n+1>maps to the most significant half of
For example, you can access the least significant half of
the elements of a vector in
Q6 by referring to
and the most significant half of the elements by referring to