Floating-point Lazy Load Multiple.
- Is an optional condition code. See Chapter 7 Condition Codes.
- Is an optional instruction width specifier. See Instruction width specifiers.
- Is the general-purpose base register.
Supported in Arm®v8‑M Main extension only.
Floating-point Lazy Load Multiple restores the contents of the Secure floating-point registers that were protected by a VLSTM instruction, and marks the floating-point context as active.
If the lazy state preservation set up by a previous VLSTM instruction is active (FPCCR.LSPACT == 1), this instruction deactivates lazy state preservation and enables access to the Secure floating-point registers.
If lazy state preservation is inactive (FPCCR.LSPACT == 0), either because lazy state preservation was not enabled (FPCCR.LSPEN == 0) or because a floating-point instruction caused the Secure floating-point register contents to be stored to memory, this instruction loads the stored Secure floating-point register contents back into the floating-point registers.
If Secure floating-point is not in use (CONTROL_S.SFPA == 0), this instruction behaves as a NOP.
This instruction is only available in Secure state, and is UNDEFINED in Non-secure state.
If the Floating-point Extension is not implemented, this instruction is available in Secure state, but behaves as a NOP.