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VRHADD
Vector Rounding Halving Add.
Syntax
VRHADD{conddatatypeQdQnQm
VRHADD{conddatatypeDdDnDm
where:
condis an optional condition code.
datatypemust be one of
S8,S16,S32,U8,U16, orU32.Qd,Qn,Qmare the destination vector, the first operand vector, and the second operand vector, for a quadword operation.
Dd,Dn,Dmare the destination vector, the first operand vector, and the second operand vector, for a doubleword operation.
Operation
VRHADD adds corresponding elements in two vectors, shifts each result
right one bit, and places the results in the destination vector. Results are rounded.