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MSR (general-purpose register to PSR)

Load an immediate value, or the contents of a general-purpose register, into the specified fields of a Program Status Register (PSR).

Syntax

MSR{cond} APSR_flags, Rm

where:

cond
is an optional condition code.
flags

specifies the APSR flags to be moved. flags can be one or more of:

nzcvq
ALU flags field mask, PSR[31:27] (User mode)
g
SIMD GE flags field mask, PSR[19:16] (User mode).
Rm

is the general-purpose register. Rm must not be PC.

Syntax on architectures other than Armv6‑M, Armv7‑M, Armv8‑M.baseline, and Armv8‑M.mainline

MSR{cond} APSR_flags, #constant

MSR{cond} psr_fields, #constant

MSR{cond} psr_fields, Rm

where:

cond
is an optional condition code.
flags

specifies the APSR flags to be moved. flags can be one or more of:

nzcvq
ALU flags field mask, PSR[31:27] (User mode)
g
SIMD GE flags field mask, PSR[19:16] (User mode).
constant
is an expression evaluating to a numeric value. The value must correspond to an 8-bit pattern rotated by an even number of bits within a 32-bit word. Not available in T32.
Rm
is the source register. Rm must not be PC.
psr

is one of:

CPSR
for use in Debug state, also deprecated synonym for APSR
SPSR
on any processor, in privileged software execution only.
fields

specifies the SPSR or CPSR fields to be moved. fields can be one or more of:

c
control field mask byte, PSR[7:0] (privileged software execution)
x
extension field mask byte, PSR[15:8] (privileged software execution)
s
status field mask byte, PSR[23:16] (privileged software execution)
f
flags field mask byte, PSR[31:24] (privileged software execution).

Syntax on architectures Armv6‑M, Armv7‑M, Armv8‑M.baseline, and Armv8‑M.mainline only

MSR{cond} psr, Rm

where:

cond
is an optional condition code.
Rm
is the source register. Rm must not be PC.
psr
can be any of: APSR, IPSR, EPSR, IEPSR, IAPSR, EAPSR, XPSR, MSP, PSP, PRIMASK, BASEPRI, BASEPRI_MAX, FAULTMASK, or CONTROL.

Usage

In User mode:

  • Use APSR to access the condition flags, Q, or GE bits.
  • Writes to unallocated, privileged or execution state bits in the CPSR are ignored. This ensures that User mode programs cannot change to privileged software execution.

Arm deprecates using MSR to change the endianness bit (E) of the CPSR, in any mode.

You must not attempt to access the SPSR when the processor is in User or System mode.

Register restrictions

You cannot use PC in A32 instructions. You can use SP for Rm in A32 instructions but this is deprecated.

You cannot use PC or SP in T32 instructions.

Condition flags

This instruction updates the flags explicitly if the APSR_nzcvq or CPSR_f field is specified.

Architectures

This instruction is available in A32 and T32.

There is no 16-bit version of this instruction in T32.

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