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PLD, PLDW, and PLI

Preload Data and Preload Instruction allow the processor to signal the memory system that a data or instruction load from an address is likely in the near future.

Syntax

PLtype{cond} [Rn {, #offset}]

PLtype{cond} [Rn, ±Rm {, shift}]

PLtype{cond} label

where:

type

can be one of:

D

Data address.

DW

Data address with intention to write.

I

Instruction address.

type cannot be DW if the syntax specifies label.

cond

is an optional condition code.

Note

cond is permitted only in T32 code, using a preceding IT instruction, but this is deprecated in the Armv8 architecture. This is an unconditional instruction in A32 code and you must not use cond.
Rn

is the register on which the memory address is based.

offset

is an immediate offset. If offset is omitted, the address is the value in Rn.

Rm

is a register containing a value to be used as the offset.

shift

is an optional shift.

label

is a PC-relative expression.

Range of offsets

The offset is applied to the value in Rn before the preload takes place. The result is used as the memory address for the preload. The range of offsets permitted is:

  • -4095 to +4095 for A32 instructions.
  • -255 to +4095 for T32 instructions, when Rn is not PC.
  • -4095 to +4095 for T32 instructions, when Rn is PC.

The assembler calculates the offset from the PC for you. The assembler generates an error if label is out of range.

Register or shifted register offset

In A32 code, the value in Rm is added to or subtracted from the value in Rn. In T32 code, the value in Rm can only be added to the value in Rn. The result is used as the memory address for the preload.

The range of shifts permitted is:

  • LSL #0 to #3 for T32 instructions.
  • Any one of the following for A32 instructions:
    • LSL #0 to #31.
    • LSR #1 to #32.
    • ASR #1 to #32.
    • ROR #1 to #31.
    • RRX.

Address alignment for preloads

No alignment checking is performed for preload instructions.

Register restrictions

Rm must not be PC. For T32 instructions Rm must also not be SP.

Rn must not be PC for T32 instructions of the syntax PLtype{cond} [Rn, ±Rm{, #shift}].

Architectures

The PLD instruction is available in A32.

The 32-bit encoding of PLD is available in T32.

PLDW is available only in the Armv7 architecture and above that implement the Multiprocessing Extensions.

PLI is available only in the Armv7 architecture and above.

There are no 16-bit encodings of these instructions in T32.

These are hint instructions, and their implementation is optional. If they are not implemented, they execute as NOPs.

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