Signed parallel halfword-wise subtraction.
is an optional condition code.
is the destination register.
are the general-purpose registers holding the operands.
This instruction subtracts each halfword of the second operand from the corresponding halfword of the first operand and writes the results into the corresponding halfwords of the destination. The results are modulo 216. It sets the APSR GE flags.
You cannot use PC for any operand.
You can use SP in A32 instructions but this is deprecated. You cannot use SP in T32 instructions.
This instruction does not affect the N, Z, C, V, or Q flags.
It sets the GE flags in the APSR as follows:
for bits[15:0] of the result.
for bits[31:16] of the result.
It sets a pair of GE flags to 1 to indicate that the corresponding result is greater than or
equal to zero. This is equivalent to a
SUBS instruction setting the N and V
condition flags to the same value, so that the GE condition passes.
You can use these flags to control a following
NoteGE[1:0] are set or cleared together, and GE[3:2] are set or cleared together.
The 32-bit instruction is available in A32 and T32.
For the Arm®v7‑M architecture, the 32-bit T32 instruction is only available in an Armv7E-M implementation.
There is no 16-bit version of this instruction in T32.