Unsigned halving parallel byte-wise addition.
is an optional condition code.
is the destination general-purpose register.
are the general-purpose registers holding the operands.
This instruction performs four unsigned integer additions on the corresponding bytes of the operands, halves the results, and writes the results into the corresponding bytes of the destination. This cannot cause overflow.
You cannot use PC for any operand.
You can use SP in A32 instructions but this is deprecated. You cannot use SP in T32 instructions.
This instruction does not affect the N, Z, C, V, Q, or GE flags.
The 32-bit instruction is available in A32 and T32.
For the Arm®v7‑M architecture, the 32-bit T32 instruction is only available in an Armv7E-M implementation.
There is no 16-bit version of this instruction in T32.