Unsigned saturating parallel halfword-wise addition.
is an optional condition code.
is the destination general-purpose register.
are the general-purpose registers holding the operands.
This instruction performs two unsigned integer additions on
the corresponding halfwords of the operands and writes the results
into the corresponding halfwords of the destination. It saturates the
results to the unsigned range 0 ≤
x ≤ 216 -1.
The Q flag is not affected even if this operation saturates.
You cannot use PC for any operand.
You can use SP in A32 instructions but this is deprecated. You cannot use SP in T32 instructions.
This instruction does not affect the N, Z, C, V, Q, or GE flags.
The 32-bit instruction is available in A32 and T32.
For the Arm®v7‑M architecture, the 32-bit T32 instruction is only available in an Armv7E-M implementation.
There is no 16-bit version of this instruction in T32.