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FMSUB

Floating-point Fused Multiply-Subtract (scalar).

Syntax

FMSUB Hd, Hn, Hm, Ha ; Half-precision

FMSUB Sd, Sn, Sm, Sa ; Single-precision

FMSUB Dd, Dn, Dm, Da ; Double-precision

Where:

Hd
Is the 16-bit name of the SIMD and FP destination register.
Hn
Is the 16-bit name of the first SIMD and FP source register holding the multiplicand.
Hm
Is the 16-bit name of the second SIMD and FP source register holding the multiplier.
Ha
Is the 16-bit name of the third SIMD and FP source register holding the minuend.
Sd
Is the 32-bit name of the SIMD and FP destination register.
Sn
Is the 32-bit name of the first SIMD and FP source register holding the multiplicand.
Sm
Is the 32-bit name of the second SIMD and FP source register holding the multiplier.
Sa
Is the 32-bit name of the third SIMD and FP source register holding the minuend.
Dd
Is the 64-bit name of the SIMD and FP destination register.
Dn
Is the 64-bit name of the first SIMD and FP source register holding the multiplicand.
Dm
Is the 64-bit name of the second SIMD and FP source register holding the multiplier.
Da
Is the 64-bit name of the third SIMD and FP source register holding the minuend.

Operation

Floating-point Fused Multiply-Subtract (scalar). This instruction multiplies the values of the first two SIMD and FP source registers, negates the product, adds that to the value of the third SIMD and FP source register, and writes the result to the SIMD and FP destination register.

This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps in the Arm Architecture Reference Manual Armv8, for Armv8‑A architecture profile.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Vd = Va + (-Vn)*Vm.

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