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FADD (vector)

Floating-point Add (vector).


FADD Vd.T, Vn.T, Vm.T ; Half-precision

FADD Vd.T, Vn.T, Vm.T ; Single-precision and double-precision



Is an arrangement specifier:

Can be one of 4H or 8H.
Single-precision and double-precision
Can be one of 2S, 4S or 2D.
Is the name of the SIMD and FP destination register.
Is the name of the first SIMD and FP source register.
Is the name of the second SIMD and FP source register.

Architectures supported (vector)

Supported in the Armv8.2 architecture and later.


Floating-point Add (vector). This instruction adds corresponding vector elements in the two source SIMD and FP registers, writes the result into a vector, and writes the vector to the destination SIMD and FP register. All the values in this instruction are floating-point values.

This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps in the Arm Architecture Reference Manual Armv8, for Armv8‑A architecture profile.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

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