You copied the Doc URL to your clipboard.

FCMGT (vector, register)

Floating-point Compare Greater than (vector).

Syntax

FCMGT Vd.T, Vn.T, Vm.T

Where:

Vd
Is the name of the SIMD and FP destination register.
T

For the vector half precision variant: is an arrangement specifier:

Vector half precision
Can be one of 4H or 8H.
Vector single-precision and double-precision
Can be one of 2S, 4S or 2D.
Vn
Is the name of the first SIMD and FP source register.
Vm
Is the name of the second SIMD and FP source register.

Architectures supported (vector)

Supported in ARMv8.2 and later.

Usage

Floating-point Compare Greater than (vector). This instruction reads each floating-point value in the first source SIMD and FP register and if the value is greater than the corresponding floating-point value in the second source SIMD and FP register sets every bit of the corresponding vector element in the destination SIMD and FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD and FP register to zero.

This instruction can generate a floating-point exception. Depending on the settings in FPCR in the ARMv8-A Architecture Reference Manual, the exception results in either a flag being set in FPSR in the ARMv8-A Architecture Reference Manual, or a synchronous exception being generated. For more information, see Floating-point exception traps in the ARMv8-A Architecture Reference Manual.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Was this page helpful? Yes No