FMAXNM (vector)
Floating-point Maximum Number (vector).
Syntax
FMAXNM
Vd.T, Vn.T, Vm.T ; Half-precision
FMAXNM
Vd.T, Vn.T, Vm.T ; Single-precision and double-precision
Where:
T-
Is an arrangement specifier:
- Half-precision
-
Can be one of
4Hor8H. - Single-precision and double-precision
-
Can be one of
2S,4Sor2D.
Vd- Is the name of the SIMD and FP destination register.
Vn- Is the name of the first SIMD and FP source register.
Vm- Is the name of the second SIMD and FP source register.
Architectures supported (vector)
Supported in the Armv8.2 architecture and later.
Usage
Floating-point Maximum Number (vector). This instruction compares corresponding vector elements in the two source SIMD and FP registers, writes the larger of the two floating-point values into a vector, and writes the vector to the destination SIMD and FP register.
NaNs are handled according to the IEEE 754-2008 standard. If one vector element is numeric and the other is a quiet NaN, the result placed in the vector is the numerical value, otherwise the result is identical to FMAX (scalar).
This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps in the Arm Architecture Reference Manual Armv8, for Armv8‑A architecture profile.
Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.