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SQDMULH (vector)

Signed saturating Doubling Multiply returning High half.

Syntax

SQDMULH Vd.T, Vn.T, Vm.T

Where:

Vd
Is the name of the SIMD and FP destination register.
T
Is an arrangement specifier, and can be one of 4H, 8H, 2S or 4S.
Vn
Is the name of the first SIMD and FP source register.
Vm
Is the name of the second SIMD and FP source register.

Usage

Signed saturating Doubling Multiply returning High half. This instruction multiplies the values of corresponding elements of the two source SIMD and FP registers, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD and FP register.

The results are truncated. For rounded results, see SQRDMULH in the ARMv8-A Architecture Reference Manual.

If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

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