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SSRA (vector)

Signed Shift Right and Accumulate (immediate).

Syntax

SSRA Vd.T, Vn.T, #shift

Where:

Vd
Is the name of the SIMD and FP destination register.
T
Is an arrangement specifier, and can be one of the values shown in Usage.
Vn
Is the name of the SIMD and FP source register.
shift
Is the right shift amount, in the range 1 to the element width in bits, and can be one of the values shown in Usage.

Usage

Signed Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD and FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD and FP register. All the values in this instruction are signed integer values. The results are truncated. For rounded results, see SRSRA in the ARMv8-A Architecture Reference Manual.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

The following table shows the valid specifier combinations:

Table 20-76 SSRA (Vector) specifier combinations

T shift
8B 1 to 8
16B 1 to 8
4H 1 to 16
8H 1 to 16
2S 1 to 32
4S 1 to 32
2D 1 to 64
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