You copied the Doc URL to your clipboard.

UADDW, UADDW2 (vector)

Unsigned Add Wide.

Syntax

UADDW{2} Vd.Ta, Vn.Ta, Vm.Tb

Where:

2
Is the second and upper half specifier. If present it causes the operation to be performed on the upper 64 bits of the registers holding the narrower elements. See <Q> in the Usage table.
Vd
Is the name of the SIMD and FP destination register.
Ta
Is an arrangement specifier, and can be one of the values shown in Usage.
Vn
Is the name of the first SIMD and FP source register.
Vm
Is the name of the second SIMD and FP source register.
Tb
Is an arrangement specifier, and can be one of the values shown in Usage.

Usage

Unsigned Add Wide. This instruction adds the vector elements of the first source SIMD and FP register to the corresponding vector elements in the lower or upper half of the second source SIMD and FP register, places the result in a vector, and writes the vector to the SIMD and FP destination register. The vector elements of the destination register and the first source register are twice as long as the vector elements of the second source register. All the values in this instruction are unsigned integer values.

The UADDW instruction extracts vector elements from the lower half of the second source register, while the UADDW2 instruction extracts vector elements from the upper half of the second source register.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

The following table shows the valid specifier combinations:

Table 20-91 UADDW, UADDW2 (Vector) specifier combinations

<Q> Ta Tb
- 8H 8B
2 8H 16B
- 4S 4H
2 4S 8H
- 2D 2S
2 2D 4S
Was this page helpful? Yes No