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UQSHRN, UQSHRN2 (vector)

Unsigned saturating Shift Right Narrow (immediate).

Syntax

UQSHRN{2} Vd.Tb, Vn.Ta, #shift

Where:

2
Is the second and upper half specifier. If present it causes the operation to be performed on the upper 64 bits of the registers holding the narrower elements. See <Q> in the Usage table.
Vd
Is the name of the SIMD and FP destination register.
Tb
Is an arrangement specifier, and can be one of the values shown in Usage.
Vn
Is the name of the SIMD and FP source register.
Ta
Is an arrangement specifier, and can be one of the values shown in Usage.
shift
Is the right shift amount, in the range 1 to the destination element width in bits, and can be one of the values shown in Usage.

Usage

Unsigned saturating Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD and FP register, right shifts each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD and FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see UQRSHRN in the ARMv8-A Architecture Reference Manual.

The UQSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the UQSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.

If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

The following table shows the valid specifier combinations:

Table 20-104 UQSHRN{2} (Vector) specifier combinations

<Q> Tb Ta shift
- 8B 8H 1 to 8
2 16B 8H 1 to 8
- 4H 4S 1 to 16
2 8H 4S 1 to 16
- 2S 2D 1 to 32
2 4S 2D 1 to 32
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