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VLDR pseudo-instruction

The VLDR pseudo-instruction loads a constant value into every element of a 64-bit Advanced SIMD vector.

Note

This description is for the VLDR pseudo-instruction only.

Syntax

VLDR{cond}.datatype Dd,=constant

where:

cond
is an optional condition code.
datatype

must be one of In, Sn, Un, or F32.

n
must be one of 8, 16, 32, or 64.
Dd
is the extension register to be loaded.
constant
is an immediate value of the appropriate type for datatype.

Usage

If an instruction (for example, VMOV) is available that can generate the constant directly into the register, the assembler uses it. Otherwise, it generates a doubleword literal pool entry containing the constant and loads the constant using a VLDR instruction.

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