Floating-point Lazy Store Multiple.
- Is an optional condition code. See Chapter 7 Condition Codes.
- Is an optional instruction width specifier. See Instruction width specifiers.
- Is the general-purpose base register.
Supported in Arm®v8‑M Main extension only.
Floating-point Lazy Store Multiple stores the contents of Secure floating-point registers to a prepared stack frame, and clears the Secure floating-point registers.
If floating-point lazy preservation is enabled (FPCCR.LSPEN == 1), then the next time a floating-point instruction other than VLSTM or VLLDM is executed:
- The contents of Secure floating-point registers are stored to memory.
- The Secure floating-point registers are cleared.
If Secure floating-point is not in use (CONTROL_S.SFPA == 0), this instruction behaves as a NOP.
This instruction is only available in Secure state, and is UNDEFINED in Non-secure state.
If the Floating-point extension is not implemented, this instruction is available in Secure state, but behaves as a NOP.