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A64 general instructions in alphabetical order

The following A64 general instructions and pseudo-instructions are supported:

Table 31. Location of general instructions
MnemonicBrief descriptionSee
ADCAdd with carryADC
ADCSAdd with carry, setting the condition flagsADCS
ADD (extended register)Add (extended register)ADD (extended register)
ADD (immediate)Add (immediate)ADD (immediate)
ADD (shifted register)Add (shifted register)ADD (shifted register)
ADDS (extended register)Add (extended register), setting the condition flagsADDS (extended register)
ADDS (immediate)Add (immediate), setting the condition flagsADDS (immediate)
ADDS (shifted register)Add (shifted register), setting the condition flagsADDS (shifted register)
ADRAddress of label at a PC-relative offsetADR
ADRL pseudo-instructionLoad a PC-relative address into a registerADRL pseudo-instruction
ADRPAddress of 4KB page at a PC-relative offsetADRP
AND (immediate)Bitwise AND (immediate)AND (immediate)
AND (shifted register)Bitwise AND (shifted register)AND (shifted register)
ANDS (immediate)Bitwise AND (immediate), setting the condition flagsANDS (immediate)
ANDS (shifted register)Bitwise AND (shifted register), setting the condition flagsANDS (shifted register)
ASR (register)Arithmetic shift right (register)ASR (register)
ASR (immediate)Arithmetic shift right (immediate)ASR (immediate)
ASRVArithmetic shift right variableASRV
ATAddress translateAT
B.condBranch conditionally to a label at a PC-relative offset, with a hint that this is not a subroutine call or returnB.cond
BBranch unconditionally to a label at a PC-relative offset, with a hint that this is not a subroutine call or returnB
BFIBitfield insert, leaving other bits unchangedBFI
BFMBitfield move, leaving other bits unchangedBFM
BFXILBitfield extract and insert at low end, leaving other bits unchangedBFXIL
BIC (shifted register)Bitwise bit clear (shifted register)BIC (shifted register)
BICS (shifted register)Bitwise bit clear (shifted register), setting the condition flagsBICS (shifted register)
BLBranch with link, calls a subroutine at a PC-relative offset, setting register X30 to PC + 4BL
BLRBranch with link to register, calls a subroutine at an address in a register, setting register X30 to PC + 4BLR
BRBranch to register, branches unconditionally to an address in a register, with a hint that this is not a subroutine returnBR
BRKSelf-hosted debug breakpointBRK
CBNZCompare and branch if nonzero to a label at a PC-relative offset, without affecting the condition flags, and with a hint that this is not a subroutine call or returnCBNZ
CBZCompare and branch if zero to a label at a PC-relative offset, without affecting the condition flags, and with a hint that this is not a subroutine call or returnCBZ
CCMN (immediate)Conditional compare negative (immediate), setting condition flags to result of comparison or an immediate valueCCMN (immediate)
CCMN (register)Conditional compare negative (register), setting condition flags to result of comparison or an immediate valueCCMN (register)
CCMP (immediate)Conditional compare (immediate), setting condition flags to result of comparison or an immediate valueCCMP (immediate)
CCMP (register)Conditional compare (register), setting condition flags to result of comparison or an immediate valueCCMP (register)
CINCConditional incrementCINC
CINVConditional invertCINV
CLREXClear exclusive monitorCLREX
CLSCount leading sign bitsCLS
CLZCount leading zero bitsCLZ
CMN (extended register)Compare negative (extended register), setting the condition flags and discarding the resultCMN (extended register)
CMN (immediate)Compare negative (immediate), setting the condition flags and discarding the resultCMN (immediate)
CMN (shifted register)Compare negative (shifted register), setting the condition flags and discarding the resultCMN (shifted register)
CMP (extended register)Compare (extended register), setting the condition flags and discarding the resultCMP (extended register)
CMP (immediate)Compare (immediate), setting the condition flags and discarding the resultCMP (immediate)
CMP (shifted register)Compare (shifted register), setting the condition flags and discarding the resultCMP (shifted register)
CNEGConditional negateCNEG
CRC32B, CRC32H, CRC32W, CRC32XCRC-32 checksum from byte, halfword, word or doublewordCRC32B, CRC32H, CRC32W, CRC32X
CRC32CB, CRC32CH, CRC32CW, CRC32CXCRC-32C checksum from byte, halfword, word, or doublewordCRC32CB, CRC32CH, CRC32CW, CRC32CX
CSELConditional select, returning the first or second inputCSEL
CSETConditional setCSET
CSETMConditional set maskCSETM
CSINCConditional select increment, returning the first input or incremented second inputCSINC
CSINVConditional select inversion, returning the first input or inverted second inputCSINV
CSNEGConditional select negation, returning the first input or negated second inputCSNEG
DCData cache operationDC
DCPS1Debug switch to exception level 1DCPS1 (A64 instruction)
DCPS2Debug switch to exception level 2DCPS2 (A64 instruction)
DCPS3Debug switch to exception level 3DCPS3 (A64 instruction)
DMBData memory barrierDMB
DRPSDebug restore process stateDRPS
DSBData synchronization barrierDSB
EON (shifted register)Bitwise exclusive OR NOT (shifted register)EON (shifted register)
EOR (immediate)Bitwise exclusive OR (immediate)EOR (immediate)
EOR (shifted register)Bitwise exclusive OR (shifted register)EOR (shifted register)
ERETReturns from an exceptionERET
EXTRExtract register from pair of registersEXTR
HINTHint instructionHINT
HLTExternal debug breakpointHLT
HVCHypervisor call to allow OS code to call the HypervisorHVC
ICInstruction cache operationIC
ISBInstruction synchronization barrierISB
LSL (register)Logical shift left (register)LSL (register)
LSL (immediate)Logical shift left (immediate)LSL (immediate)
LSLVLogical shift left variableLSLV
LSR (register)Logical shift right (register)LSR (register)
LSR (immediate)Logical shift right (immediate)LSR (immediate)
LSRVLogical shift right variableLSRV
MADDMultiply-addMADD
MNEGMultiply-negateMNEG
MOV (to or from SP)Move between register and stack pointerMOV (to or from SP)
MOV (inverted wide immediate)Move inverted 16-bit immediate to registerMOV (inverted wide immediate)
MOV (wide immediate)Move 16-bit immediate to registerMOV (wide immediate)
MOV (bitmask immediate)Move bitmask immediate to registerMOV (bitmask immediate)
MOV (register)Move register to registerMOV (register)
MOVKMove 16-bit immediate into register, keeping other bits unchangedMOVK
MOVL pseudo-instructionLoad a registerMOVL pseudo-instruction
MOVNMove inverse of shifted 16-bit immediate to registerMOVN
MOVZMove shifted 16-bit immediate to registerMOVZ
MRSMove from system registerMRS
MSR (immediate)Move immediate to process state fieldMSR (immediate)
MSR (register)Move to system registerMSR (register)
MSUBMultiply-subtractMSUB
MULMultiplyMUL
MVNBitwise NOT (shifted register)MVN
NEG (shifted register)NegateNEG (shifted register)
NEGSNegate, setting the condition flagsNEGS
NGCNegate with carryNGC
NGCSNegate with carry, setting the condition flagsNGCS
NOPNo operationNOP
ORN (shifted register)Bitwise inclusive OR NOT (shifted register)ORN (shifted register)
ORR (immediate)Bitwise inclusive OR (immediate)ORR (immediate)
ORR (shifted register)Bitwise inclusive OR (shifted register)ORR (shifted register)
RBITReverse bit orderRBIT
RETReturn from subroutine, branches unconditionally to an address in a register, with a hint that this is a subroutine returnRET
REVReverse bytesREV
REV16Reverse bytes in 16-bit halfwordsREV16
REV32Reverse bytes in 32-bit wordsREV32
ROR (immediate)Rotate right (immediate)ROR (immediate)
ROR (register)Rotate right (register)ROR (register)
RORVRotate right variableRORV
SBCSubtract with carrySBC
SBCSSubtract with carry, setting the condition flagsSBCS
SBFIZSigned bitfield insert in zero, with sign replication to left and zeros to rightSBFIZ
SBFMSigned bitfield move, with sign replication to left and zeros to rightSBFM
SBFXSigned bitfield extractSBFX
SDIVSigned divideSDIV
SEVSend eventSEV
SEVLSend event locallySEVL
SMADDLSigned multiply-add longSMADDL
SMCSupervisor call to allow OS or Hypervisor code to call the Secure MonitorSMC
SMNEGLSigned multiply-negate longSMNEGL
SMSUBLSigned multiply-subtract longSMSUBL
SMULHSigned multiply highSMULH
SMULLSigned multiply longSMULL
SUB (extended register)Subtract (extended register)SUB (extended register)
SUB (immediate)Subtract (immediate)SUB (immediate)
SUB (shifted register)Subtract (shifted register)SUB (shifted register)
SUBS (extended register)Subtract (extended register), setting the condition flagsSUBS (extended register)
SUBS (immediate)Subtract (immediate), setting the condition flagsSUBS (immediate)
SUBS (shifted register)Subtract (shifted register), setting the condition flagsSUBS (shifted register)
SVCSupervisor call to allow application code to call the OSSVC
SXTBSigned extend byteSXTB
SXTHSigned extend halfwordSXTH
SXTWSigned extend wordSXTW
SYSSystem instructionSYS
SYSLSystem instruction with resultSYSL
TBNZTest bit and branch if nonzero to a label at a PC-relative offset, without affecting the condition flags, and with a hint that this is not a subroutine call or returnTBNZ
TBZTest bit and branch if zero to a label at a PC-relative offset, without affecting the condition flags, and with a hint that this is not a subroutine call or returnTBZ
TLBITLB invalidate operationTLBI
TST (immediate)Test bits (immediate), setting the condition flags and discarding the resultTST (immediate)
TST (shifted register)Test bits (shifted register), setting the condition flags and discarding the resultTST (shifted register)
UBFIZUnsigned bitfield insert in zero, with zeros to left and rightUBFIZ
UBFMUnsigned bitfield move, with zeros to left and rightUBFM
UBFXUnsigned bitfield extractUBFX
UDIVUnsigned divideUDIV
UMADDLUnsigned multiply-add longUMADDL
UMNEGLUnsigned multiply-negate longUMNEGL
UMSUBLUnsigned multiply-subtract longUMSUBL
UMULHUnsigned multiply highUMULH
UMULLUnsigned multiply longUMULL
UXTBUnsigned extend byteUXTB
UXTHUnsigned extend halfwordUXTH
WFEWait for eventWFE
WFIWait for interruptWFI
YIELDYield hintYIELD

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