You copied the Doc URL to your clipboard.

B, BL, BX, and BLX

Branch, Branch with Link, Branch and exchange instruction set, Branch with Link and exchange instruction set.


op1{cond}{.W} label
op2{cond} Rm



is one of:




Branch with link.


Branch with link, and exchange instruction set.


is one of:


Branch and exchange instruction set.


Branch with link, and exchange instruction set.


is an optional condition code. cond is not available on all forms of this instruction.


is an optional instruction width specifier to force the use of a 32-bit B instruction in T32.


is a PC-relative expression.


is a register containing an address to branch to.


All these instructions cause a branch to label, or to the address contained in Rm. In addition:

  • The BL and BLX instructions copy the address of the next instruction into LR (R14, the link register).

  • The BX and BLX instructions can change the instruction set.

    BLX label always changes the instruction set. It changes a processor in A32 state to T32 state, or a processor in T32 state to A32 state.

    BX Rm and BLX Rm derive the target instruction set from bit[0] of Rm:

    • If bit[0] of Rm is 0, the processor changes to, or remains in, A32 state.

    • If bit[0] of Rm is 1, the processor changes to, or remains in, T32 state.


There are no equivalent instructions to BX and BLX to change between AArch32 and AArch64 state. The only way to change execution state is by a change of exception level.

Instruction availability and branch ranges

Table 8 shows the instructions that are available in A32 and T32 state. Instructions that are not shown in this table are not available.

Table 8. Branch instruction availability and range
InstructionA3216-bit T32 encoding32-bit T32 encoding
B label±32MB±2KB±16MB[a]
B{cond} label±32MB-252 to +258±1MBa
BL label±32MB±4MB [b]±16MB
BL{cond} label±32MB--
BX Rm AvailableAvailableUse 16-bit
BX{cond} Rm Available--
BLX label±32MB±4MB [b]±16MB
BLX RmAvailableAvailableUse 16-bit
BLX{cond} RmAvailable--

[a] Use .W to instruct the assembler to use this 32-bit instruction.

[b] This is an instruction pair.

Extending branch ranges

Machine-level B and BL instructions have restricted ranges from the address of the current instruction. However, you can use these instructions even if label is out of range. Often you do not know where the linker places label. When necessary, the linker adds code to enable longer branches. The added code is called a veneer.

B in T32

You can use the .W width specifier to force B to generate a 32-bit instruction in T32 code.

B.W always generates a 32-bit instruction, even if the target could be reached using a 16-bit instruction.

For forward references, B without .W always generates a 16-bit instruction in T32 code, even if that results in failure for a target that could be reached using a 32-bit T32 instruction.

Register restrictions

Using PC for Rm in the A32 BX instruction is deprecated. You cannot use PC in other A32 instructions.

You can use PC for Rm in the T32 BX instruction. You cannot use PC in other T32 instructions.

Using SP for Rm in these A32 instructions is deprecated.

Using SP for Rm in the T32 BX and BLX instructions is deprecated. You cannot use SP in the other T32 instructions.

Condition flags

These instructions do not change the flags.


See Table 8 for details of availability of these instructions in both instruction sets.


    B       loopA
    BLE     ng+8
    BL      subC
    BLLT    rtX
    BEQ     {PC}+4  ; #0x8004