Type 3 image structure, multiple load regions and non-contiguous execution regions
A Type 3 image is similar to a Type 2 image except that the single load region is split into multiple root load regions.
The following figure shows the load and execution view for a Type 3 image:
Figure 3-4 Simple Type 3 image
Use the following command for images of this type:
armlink --cpu=8-A.32 --split --ro_base 0x8000 --rw_base 0xE000
In the load view, the first load region consists of the RO output section, and the second load region consists of the RW output section. The ZI output section does not exist at load time. It is created before execution, using the description of the output section contained in the image file.
In the execution view, the first execution region contains the RO output section, the second execution region contains the RW output section, and the third execution region contains the ZI output section.
The execution address of the RO region is the same as its load address, so the contents of the RO output section do not have to be moved or copied from their load address to their execution address. Both RO and RW are root regions.
The execution address of the RW region is also the same as its load address, so the contents of the RW output section are not moved from their load address to their execution address. However, the ZI output section is created at run-time and is placed contiguously with the RW region.
Specify the load and execution address using the following linker options:
Instructs armlink to set the load and execution address of the region containing the RO section at a four-byte aligned
, for example, the address of the first location in ROM. If you do not use the
--ro_baseoption to specify the address, the default value of
is used by
Instructs armlink to set the execution address of the region containing the RW output section at a four-byte aligned
. If this option is used with
--split, this specifies both the load and execution addresses of the RW region, for example, a root region.
Splits the default single load region, that contains both the RO and RW output sections, into two root load regions:
One containing the RO output section.
One containing the RW output section.
You can then place them separately using