The division routine supplied with the ARM libraries provides good overall performance. However, the amount of time required to perform a division depends on the input values. For example, a division that generates a four-bit quotient might require only 12 cycles while a 32-bit quotient might require 96 cycles. Depending on your target, some applications require a faster worst-case cycle count at the expense of lower average performance. For this reason, the ARM library provides two divide routines.
The real-time routine:
Is faster than the standard division routine for larger quotients.
Is slower than the standard division routine for typical quotients.
Returns the same results.
Does not require any change in the surrounding code.
AArch64 state processors support hardware floating-point divide, so they do not require the library divide routines.