GIC_400 - about
This LISA+ component is a model of the GIC-400 Generic Interrupt Controller (GIC), and includes a Virtualized Generic Interrupt Controller (VGIC).
It is a wrapper that permits easier configuration of the v7_VGIC component that supports parameterized configuration.
The GIC-400 has several memory-mapped interfaces at the same address. The
processor that is communicating with the GIC-400 banks them. The GIC-400 must be able to
distinguish from which processor a transaction originates. In the hardware, the AUSER
fields on AXI supply this information to the GIC-400. In Fast Models, there is no exact
equivalent to this field. However, each transaction has a
master_id that the model can use to identify the originating
ARM® clusters assign the
master_id as follows:
- Bits[31:16]: SBZ (which the GIC-400 ignores).
- Bits[5:2]: CLUSTERID.
- Bits[1:0]: cpu_id within cluster.
CLUSTERID is the 4-bit field that either a parameter on the processor
sets or a value on the
clusterid port drives. CPUID is
the core number within the cluster. CLUSTERID appears in the CP15 register space as part
of the MPIDR register.
The ARM architecture suggests that each cluster in the system is given a
different CLUSTERID. This distinction is essential for the VGIC to identify the cluster.
The parameters in the GIC-400 component permit it to construct the map of
master_id to interface number.
Processor interfaces that the GIC-400 supports have these parameters:
N is the interface number (0-7). The
core_id tell the GIC-400
to map that cluster or core combination to interface N.
GIC-400 has some input and output ports that pair with a particular processor interface.
irqcpupin wires to the
irqport of the corresponding processor.
cntpnsirqpin from the processor wires to a
cntpnsirqpin on GIC-400 to transport a Private Peripheral Interrupt (PPI) from the processor to the GIC-400.
parameter supports clusters that can have variable numbers of cores. It tells the
GIC-400 that to send to or receive a signal from the processor that is attached to
interface N, it must use these pins:
legacyfiq are not signals from the processor but are signals into the
GIC-400 from the legacy interrupt system. They are wired to PPIs. If the control
registers of the GIC-400 are set up in particular ways, they can also bypass the
GIC-400. See the ARM Generic Interrupt Controller Architecture
version 2.0 Architecture Specification for more information.
The fabric between the clusters and the GIC might remap the
master_id of a transaction. If so, then the GIC might lose
the ability to identify the originating processor. The fabrics that ARM ships in Fast
Models perform no such transformation.
The comparison that the GIC-400 performs on the
master_id is only on the bottom 6 bits of the
master_id. It ignores the rest. If you are writing your own fabric and do
not properly propagate the
master_id or transform it,
the GIC-400 might not be able to identify the processor. The source code for the GIC_400
component can be examined to see how it might be adapted for it to understand different
The GIC-400 model has these limitations:
- Reads and writes to GICD_ISACTIVERn/GICD_ICACTIVERn/GICD_ISPENDRn/GICD_ICPENDRn might not work as expected unless there is a configured target in GICD_ICFGRm.
- Some of the interaction of GICD_CTLR.EnableGrpX and level sensitive interrupts might not work entirely correctly.
- It does not model the signals nIRQOUT/nFIQOUT.
- It models interrupts with positive logic, rather than the negative logic that the hardware uses. Hence, the signal pins omit the "n" prefix in their names.