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PL041_AACI - registers

This section describes the registers.


Table 1. PL041_AACI registers
Name Offset Access Description
RXCR1 00 Read/write FIFO1 receive control
TXCR1 04 Read/write FIFO1 transmit control
SR1 08 Read/write Channel 1 status
ISR1 0C Read/write Channel 1 interrupt status
IE1 10 Read/write Channel 1 interrupt enable
RXCR2 14 Read/write FIFO2 receive control
TXCR2 18 Read/write FIFO2 transmit control
SR2 1C Read/write Channel 2 status
ISR2 20 Read/write Channel 2 interrupt status
IE2 24 Read/write Channel 2 interrupt enable
RXCR3 28 Read/write FIFO3 receive control
TXCR3 2C Read/write FIFO3 transmit control
SR3 30 Read/write Channel 3 status
ISR3 34 Read/write Channel 3 interrupt status
IE3 38 Read/write Channel 3 interrupt enable
RXCR4 3C Read/write FIFO4 receive control
TXCR4 40 Read/write FIFO4 transmit control
SR4 44 Read/write Channel 4 status
ISR4 48 Read/write Channel 4 interrupt status
IE4 4C Read/write Channel 4 interrupt enable
SL1RX 50 Read/write Slot 1 receive data
SL1TX 54 Read/write Slot 1 transmit data
SL2RX 58 Read/write Slot 2 receive data
SL2TX 5C Read/write Slot 2 transmit data
SL12RX 60 Read/write Slot 12 receive data
SL12TX 64 Read/write Slot 12 transmit data
LSFR 68 Read/write Slot flag register
SLISTAT 6C Read/write Slot interrupt status
SLIEN 70 Read/write Slot interrupt enable
ALLINTCLR 74 Write only All interrupts clear
MAINCR 78 Read/write Main control
RESET 7C Read/write Reset control
SYNC 80 Read/write Sync control
ALLINTS 84 Read/write All FIFO interrupts status
MAINFR 88 Read/write Main flags register