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PL061_GPIO - registers

This section describes the registers.

Table 1. PL061_GPIO registers
Name Offset Access Description
GPIODATA 0x000 - 3FC Read/write GPIO prime data register. The address offsets serve as a mask. Only bits[11:2] are valid as the mask.1
GPIODIR 400 Read/write Data direction register. Set for output, clear for input.
GPIOIS 404 Read/write Interrupt sense register. Set for level trigger, clear for edge trigger.
GPIOIBE 408 Read/write Bits set, both edges on corresponding pin trigger and interrupt.
GPIOIEV 40C Read/write Interrupt event register. Bit set for rising edge or high level trigger.
GPIOIE 410 Read/write Interrupt mask register.
GPIORIS 414 Read Raw interrupt status register.
GPIOMIS 418 Read Masked interrupt status register.
GPIOIC 41C Write Interrupt clear register.
GPIOAFSEL 420 Read/write Mode control select.
GPIOPeriphID0 fe0 Read Peripheral ID register.
GPIOPeriphID1 fe4 Read Peripheral ID register.
GPIOPeriphID2 fe8 Read Peripheral ID register.
GPIOPeriphID3 fec Read Peripheral ID register.
GPIOPCellID0 ff0 Read PrimeCell ID register.
GPIOPCellID1 ff4 Read PrimeCell ID register.
GPIOPCellID2 ff8 Read PrimeCell ID register.
GPIOPCellID3 ffc Read PrimeCell ID register.


For writes, values written to the registers are transferred onto the GPOIT pins if the respective pins have been configured as output ports. Set certain pins in GPIO_Mask to high to enable writing. A similar process applies to reads.