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PL080_DMAC - ports

This section describes the ports.

Table 1. PL080_DMAC ports
Name Protocol Type Description
pvbus_s PVBus Slave Slave bus for register accesses
clk_in ClockSignal Slave Clock signal to control DMA transfer rate
reset_in Signal Slave Reset signal
pvbus0_m PVBus Master Master bus interface 0 for DMA transfers
pvbus1_m PVBus Master Master bus interface 1 for DMA transfers
interr Signal Master DMA error interrupt signal
inttc Signal Master DMA terminal count signal
intr Signal Master Combined DMA error and terminal count signal
dma_port[16] PL080_DMAC_DmaPortProtocol Slave Peripheral handshake ports

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