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PL110_CLCD - ports

This section describes the ports.

Table 1. PL110_CLCD ports
Name Protocol Type Description
pvbus PVBus Slave Slave port for connection to PV bus master/decoder
intr Signal Master Interrupt signaling for flyback events
clk_in ClockSignal Slave Master clock input, typically 24MHz, to drive pixel clock timing
display LCD Master Connection to visualization component
control Value Slave Auxiliary control register 1
pvbus_m PVBus Master DMA port for video data

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