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PL110_CLCD - registers

This section describes the registers.


Table 1. PL110_CLCD registers
Name Offset Access Description
LCDTiming0 000 Read/write Horizontal timing
LCDTiming1 004 Read/write Vertical timing
LCDTiming2 008 Read/write Clock and polarity control
LCDTiming3 00C Read/write Line end control
LCDUPBASE 010 Read/write Upper panel frame base address
LCDLPBASE 014 Read/write Lower panel frame base address
LCDIMSC 018 Read/write Interrupt mask
LCDControl 01C Read/write Control
LCDRIS 020 Read only Raw interrupt status
LCDMIS 024 Read only Masked interrupt status
LCDICR 028 Write only Interrupt clear
LCDIPCURR 02C Read only Upper panel current address
LCDLPCURR 030 Read only Lower panel current address
LCDPalette 0x200-400 Read/write Palette registers
LCDPeriphID0 fe0 Read Peripheral ID register
LCDPeriphID1 fe4 Read Peripheral ID register
LCDPeriphID2 fe8 Read Peripheral ID register
LCDPeriphID3 fec Read Peripheral ID register
LCDPCellID0 ff0 Read PrimeCell ID register
LCDPCellID1 ff4 Read PrimeCell ID register
LCDPCellID2 ff8 Read PrimeCell ID register
LCDPCellID3 ffc Read PrimeCell ID register

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