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PL370_HDLCD - ports

This section describes the ports.


Table 1. PL370_HDLCD ports
Name Protocol Type Description
clk_in ClockSignal Slave Master clock input, typically 24MHz, to drive pixel clock timing.
display LCD Master Connection to visualization component
intr Signal Master Interrupt signaling line for flyback events
pvbus PVBus Slave Slave port for connection to PV bus master/decoder
pvbus_m PVBus Master DMA port for collecting video data from memory