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ARMCortexA9MPxnCT - registers This component provides the registers that the Technical Reference Manual (TRM) specifies except for the integration and test registers.
ARMCortexA9MPxnCT - caches
This component implements L1 cache as architecturally defined, but does not implement L2 cache. If you require L2 cache you can add a PL310 Level 2 Cache Controller component.