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DP500 - ports

This section describes the ports.

Table 1. DP500 ports
Name Protocol Type Description
clk_in ClockSignal Slave Master clock input, typically 12.6MHz, to drive pixel clock timing.
display LCD Master Connection to visualization component.
intr Signal Master Interrupt signaling from display engine.
intr_se Signal Master Interrupt signaling from scaling engine.
pvbus_m PVBus Master DMA port for video data.
pvbus_s PVBus Slave Slave port for connection for APB access.
reset_signal Signal Slave Slave port for external reset line.

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