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PL022_SSP - ports

This section describes the ports.


Table 1. PL022_SSP ports
Name Protocol Type Description
clk ClockSignal Slave Main PrimeCell SSP clock input
clkin ClockSignal Slave PrimeCell SSP clock input
pvbus PVBus Slave Slave port for connection to PV bus master/decoder
rxd ValueState Slave PrimeCell SSP receive data
clkout ClockSignal Master Clock output
intr Signal Master Interrupt signaling
rorintr Signal Master Receive overrun interrupt
rtintr Signal Master Receive timeout interrupt1
rx_dma_port PL080_DMAC_DmaPortProtocol Master PrimeCell SSP receive DMA port
rxintr Signal Master Receive FIFO service request port
tx_dma_port PL080_DMAC_DmaPortProtocol Master PrimeCell SSP transmit DMA port
txd ValueState Master PrimeCell SSP transmit data
txintr Signal Master Transmit FIFO service request

1

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