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SP810_SysCtrl - ports

This section describes the ports.


Table 1. SP810_SysCtrl ports
Name Protocol Type Description
clk_in ClockSignal Slave Clock input
hclkdivsel 1 ValueState Master Define the processor clock/bus clock ratio.
npor 1 Signal Slave Power on reset
pll_en 1 Signal Master PLL enable output
pvbus PVBus Slave Slave port for connection to PV bus master/decoder
ref_clk_in ClockSignal Slave Clock source used by the Timer and Watchdog modules.
sleep_mode 1 Signal Master Control clocks for SLEEP mode.
timer_clk_en[0] ClockRateControl Master Timer clock enable 0
timer_clk_en[1] ClockRateControl Master Timer clock enable 1
timer_clk_en[2] ClockRateControl Master Timer clock enable 2
timer_clk_en[3] ClockRateControl Master Timer clock enable 3
remap_clear StateSignal Master Remap clear request output
remap_stat 1 StateSignal Slave Remap status input
sys_mode 1 ValueState Slave Present system mode
sys_stat 1 ValueState Slave System status input
wd_clk_en 1 Signal Master Watchdog module clock enable output
wd_en 1 Signal Slave Watchdog module enable input

1 Not fully implemented. Using this port has unpredictable results.