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TZC_400 - about

This LISA+ component is a model of r0p1 of the ARM® TZC-400 CoreLink™ TZC-400 TrustZone® Address Space Controller.

The TZC-400 determines, under software control, whether a particular bus master is permitted to issue Non-secure accesses to a particular physical address.

The component has:

  • Eight address regions in addition to the base region, region 0.
  • A programmable control block for security-access permissions configuration through the Advanced Peripheral Bus (APB).
  • Up to four address filters that share common set region set-up registers.
  • Software configurable permission check failure reporting and interrupt signaling.
  • Filtering with a Non-Secure Access ID (NSAID).
  • A gate keeper, to allow or block accesses to the filter unit.
  • Configurable reset values of region configuration registers and other key configuration registers.

Unlike the hardware, it does not have:

  • Asynchronous clocks. The model does not need clocks for data transfer, or clock signals.
  • QoS Virtual Network (QVN) support. Specifically, it does not implement the vnet bits[27:24] in FAIL_ID_<x> registers.
  • Fast Path and Fast Path ID. In the model, transactions occur at similar speeds.
  • 256 outstanding accesses globally for each read or write Normal Paths and configurable 8, 16, or 32 outstanding accesses on Fast Path read access. The model does not support QVN, and this concept is meaningless for a PV level model.
  • Configurable address bus width, data bus width, transaction ID tag, and USER bus width. A single bus implementation, PVBus, covers these AXI bus hardware implementation details.